An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/JayakumarK03
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2003
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An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.
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MTCMOS, leakage current, standard cells, standby current
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An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.
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