A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/JoshiKKWC07
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A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
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SRAM, booster circuit, low power, yield
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A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies.
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