A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/KilGK06
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2006
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A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.
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capacitive boosting, clock skew, global interconnect, sub-threshold circuit, variation tolerance
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A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.
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