Experimental measurement of a novel power gating structure with intermediate power saving mode.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/KimKKS04
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2004
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Experimental measurement of a novel power gating structure with intermediate power saving mode.
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clock gating, ground bounce, inductive noise, power gating, system-on-a-chip (SOC) design, wake-up latency
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Experimental measurement of a novel power gating structure with intermediate power saving mode.
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