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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/KimPCP06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ilhyun_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kiyoung_Choi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yoonjin_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yunheung_Paek>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1165573.1165646>
foaf:homepage <https://doi.org/10.1145/1165573.1165646>
dc:identifier DBLP conf/islped/KimPCP06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1165573.1165646 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ilhyun_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kiyoung_Choi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yoonjin_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yunheung_Paek>
swrc:pages 310-315 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/KimPCP06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/KimPCP06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2006.html#KimPCP06>
rdfs:seeAlso <https://doi.org/10.1145/1165573.1165646>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject coarse-grained reconfigurable architecture (CGRA), configuration cache, context pipelining, loop pipelining, low power, spatial mapping, system-on-chip (SoC), temporal mapping (xsd:string)
dc:title Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document