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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/KoBN95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Poras_T._Balsara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uming_Ko>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F224081.224090>
foaf:homepage <https://doi.org/10.1145/224081.224090>
dc:identifier DBLP conf/islped/KoBN95 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F224081.224090 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Energy optimization of multi-level processor cache architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Poras_T._Balsara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uming_Ko>
swrc:pages 45-49 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/KoBN95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/KoBN95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped1995.html#KoBN95>
rdfs:seeAlso <https://doi.org/10.1145/224081.224090>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:title Energy optimization of multi-level processor cache architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document