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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/LinHHR06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lei_He_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vijay_Raghunat>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yan_Lin_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Hu_0002>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1165573.1165613>
foaf:homepage <https://doi.org/10.1145/1165573.1165613>
dc:identifier DBLP conf/islped/LinHHR06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1165573.1165613 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lei_He_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vijay_Raghunat>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yan_Lin_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Hu_0002>
swrc:pages 168-173 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/LinHHR06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/LinHHR06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2006.html#LinHHR06>
rdfs:seeAlso <https://doi.org/10.1145/1165573.1165613>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject FPGA, low power, time slack (xsd:string)
dc:title An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document