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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/MahalingamRH06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Justin_E._Harlow_III>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/N._Ranganathan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Venkataraman_Mahalingam>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1165573.1165614>
foaf:homepage <https://doi.org/10.1145/1165573.1165614>
dc:identifier DBLP conf/islped/MahalingamRH06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1165573.1165614 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label A novel approach for variation aware power minimization during gate sizing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Justin_E._Harlow_III>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/N._Ranganathan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Venkataraman_Mahalingam>
swrc:pages 174-179 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/MahalingamRH06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/MahalingamRH06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2006.html#MahalingamRH06>
rdfs:seeAlso <https://doi.org/10.1145/1165573.1165614>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:title A novel approach for variation aware power minimization during gate sizing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document