A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/MiuraAW01
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/islped/MiuraAW01
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kazushige_Ayukawa
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Seiji_Miura
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Takao_Watanabe
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F383082.383183
>
foaf:
homepage
<
https://doi.org/10.1145/383082.383183
>
dc:
identifier
DBLP conf/islped/MiuraAW01
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F383082.383183
(xsd:string)
dcterms:
issued
2001
(xsd:gYear)
rdfs:
label
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kazushige_Ayukawa
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Seiji_Miura
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Takao_Watanabe
>
swrc:
pages
358-363
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/islped/2001
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/islped/MiuraAW01/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/islped/MiuraAW01
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/islped/islped2001.html#MiuraAW01
>
rdfs:
seeAlso
<
https://doi.org/10.1145/383082.383183
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/islped
>
dc:
subject
SDRAM controller, active-standby mode, standby mode
(xsd:string)
dc:
title
A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document