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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/NakataOKY10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Kawaguchi_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Yoshimoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shunsuke_Okumura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yohei_Nakata>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1840845.1840888>
foaf:homepage <https://doi.org/10.1145/1840845.1840888>
dc:identifier DBLP conf/islped/NakataOKY10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1840845.1840888 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Kawaguchi_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Yoshimoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shunsuke_Okumura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yohei_Nakata>
swrc:pages 219-224 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/NakataOKY10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/NakataOKY10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2010.html#NakataOKY10>
rdfs:seeAlso <https://doi.org/10.1145/1840845.1840888>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject cache memory, fine-grain control, low power, low voltage, microarchitecture, variation (xsd:string)
dc:title 0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document