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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/NeveFSLH02>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Denis_Flandre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerhard_Hellner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Helmut_Schettler>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_Ludwig_0004>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F566408.566438>
foaf:homepage <https://doi.org/10.1145/566408.566438>
dc:identifier DBLP conf/islped/NeveFSLH02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F566408.566438 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Design of a branch-based 64-bit carry-select adder in 0.18 ¬Ķm partially depleted SOI CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Amaury_N%E2%88%9A%C2%AEve>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Denis_Flandre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerhard_Hellner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Helmut_Schettler>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_Ludwig_0004>
swrc:pages 108-111 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2002.html#NeveFSLH02>
rdfs:seeAlso <https://doi.org/10.1145/566408.566438>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject SOI technology, circuit Design, logic design styles (xsd:string)
dc:title Design of a branch-based 64-bit carry-select adder in 0.18 ¬Ķm partially depleted SOI CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document