A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/PallottaCT00
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2000
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A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.
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SDH, clock recovery, low power, optical communications
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A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.
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