Vt balancing and device sizing towards high yield of sub-threshold static logic gates.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/PuGCH07
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Vt balancing and device sizing towards high yield of sub-threshold static logic gates.
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sub-threshold, variability
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Vt balancing and device sizing towards high yield of sub-threshold static logic gates.
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