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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/PuGCH07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Henk_Corporaal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_de_Jesus_Pineda_de_Gyvez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yajun_Ha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu_Pu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1283780.1283857>
foaf:homepage <https://doi.org/10.1145/1283780.1283857>
dc:identifier DBLP conf/islped/PuGCH07 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1283780.1283857 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Vt balancing and device sizing towards high yield of sub-threshold static logic gates. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Henk_Corporaal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_de_Jesus_Pineda_de_Gyvez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yajun_Ha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu_Pu>
swrc:pages 355-358 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/PuGCH07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/PuGCH07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2007.html#PuGCH07>
rdfs:seeAlso <https://doi.org/10.1145/1283780.1283857>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject sub-threshold, variability (xsd:string)
dc:title Vt balancing and device sizing towards high yield of sub-threshold static logic gates. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document