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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/RasquinhaCCMY10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dhruv_Choudhary>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitchelle_Rasquinha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Subho_Chatterjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_Yalamanchili>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1840845.1840931>
foaf:homepage <https://doi.org/10.1145/1840845.1840931>
dc:identifier DBLP conf/islped/RasquinhaCCMY10 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1840845.1840931 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label An energy efficient cache design using spin torque transfer (STT) RAM. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dhruv_Choudhary>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitchelle_Rasquinha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Subho_Chatterjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_Yalamanchili>
swrc:pages 389-394 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/RasquinhaCCMY10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/RasquinhaCCMY10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2010.html#RasquinhaCCMY10>
rdfs:seeAlso <https://doi.org/10.1145/1840845.1840931>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject (STT)RAM, cache design, memory technologies (xsd:string)
dc:title An energy efficient cache design using spin torque transfer (STT) RAM. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document