A 65-nm pulsed latch with a single clocked transistor.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/Saint-LaurentMB07
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2007
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A 65-nm pulsed latch with a single clocked transistor.
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low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
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A 65-nm pulsed latch with a single clocked transistor.
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