Efficient scan-based BIST scheme for low power testing of VLSI chips.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/Shah06
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2006
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Efficient scan-based BIST scheme for low power testing of VLSI chips.
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partial scan, scan, switching activity, test length, test-per-clock, test-per-scan
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Efficient scan-based BIST scheme for low power testing of VLSI chips.
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