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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/TachibanaKNKYMG95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M._Tachibana>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masaaki_Yamada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nobuyuki_Goto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Norman_Kojima>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R._Nojima>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Kurosawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takashi_Mitsuhashi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F224081.224109>
foaf:homepage <https://doi.org/10.1145/224081.224109>
dc:identifier DBLP conf/islped/TachibanaKNKYMG95 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F224081.224109 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Power and area optimization by reorganizing CMOS complex gate circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M._Tachibana>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masaaki_Yamada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nobuyuki_Goto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Norman_Kojima>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R._Nojima>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Kurosawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takashi_Mitsuhashi>
swrc:pages 155-160 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/1995>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped1995.html#TachibanaKNKYMG95>
rdfs:seeAlso <https://doi.org/10.1145/224081.224109>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:title Power and area optimization by reorganizing CMOS complex gate circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document