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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/islped/TaylorS04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Herman_Schmit>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R._Reed_Taylor>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1013235.1013260>
foaf:homepage <https://doi.org/10.1145/1013235.1013260>
dc:identifier DBLP conf/islped/TaylorS04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1013235.1013260 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Creating a power-aware structured ASIC. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Herman_Schmit>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R._Reed_Taylor>
swrc:pages 74-77 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/islped/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/islped/TaylorS04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/islped/TaylorS04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/islped/islped2004.html#TaylorS04>
rdfs:seeAlso <https://doi.org/10.1145/1013235.1013260>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:subject VPGA, gate sizing, low-power, power optimization, structured ASIC, voltage scaling (xsd:string)
dc:title Creating a power-aware structured ASIC. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document