Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/WangLLYW06
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2006
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Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
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leakage current reduction, mixed integer linear programming, two-phase fine-grain sleep transistor insertion
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Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.
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