Low power sequential circuit design by using priority encoding and clock gating. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/islped/WuP00>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Massoud_Pedram>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Xunwei_Wu>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1145%2F344166.344557>
foaf:homepage	<https://doi.org/10.1145/344166.344557>
dc:identifier	DBLP conf/islped/WuP00 (xsd:string)
dc:identifier	DOI doi.org%2F10.1145%2F344166.344557 (xsd:string)
dcterms:issued	2000 (xsd:gYear)
rdfs:label	Low power sequential circuit design by using priority encoding and clock gating. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Massoud_Pedram>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Xunwei_Wu>
swrc:pages	143-148 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/islped/2000>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/islped/WuP00/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/islped/WuP00>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/islped/islped2000.html#WuP00>
rdfs:seeAlso	<https://doi.org/10.1145/344166.344557>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/islped>
dc:title	Low power sequential circuit design by using priority encoding and clock gating. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document