A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/islped/YounKK07
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2007
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A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.
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L2 cache, architecture, chip multiprocessors (CMPS), embedded systems, low-power, performance
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A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.
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