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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/DatlaTHH09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dave_Henderson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luther_Hendrix>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitchell_A._Thornton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satyendra_R._Datla>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.2009.66>
foaf:homepage <https://doi.org/10.1109/ISMVL.2009.66>
dc:identifier DBLP conf/ismvl/DatlaTHH09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.2009.66 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dave_Henderson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luther_Hendrix>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitchell_A._Thornton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satyendra_R._Datla>
swrc:pages 256-261 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/DatlaTHH09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/DatlaTHH09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl2009.html#DatlaTHH09>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.2009.66>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document