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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/DebnathS99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Debatosh_Debnath>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Sasao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.1999.779702>
foaf:homepage <https://doi.org/10.1109/ISMVL.1999.779702>
dc:identifier DBLP conf/ismvl/DebnathS99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.1999.779702 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Debatosh_Debnath>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Sasao>
swrc:pages 99-104 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/DebnathS99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/DebnathS99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl1999.html#DebnathS99>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.1999.779702>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:subject Three-level network, logic minimization, adder, multiple-valued logic, programmable logic array. (xsd:string)
dc:title Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document