Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/GonzalezBKM00
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Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.
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signed-digit adder, redundant number systems, negative differential-resistance devices, NDR devices, resonant-tunneling diodes, RTDs, multiple-valued logic
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Standard CMOS Implementation of a Multiple-Valued Logic Signed-Digit Adder Based on Negative Differential-Resistance Devices.
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