[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/HanyuKK00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiromitsu_Kimura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michitaka_Kameyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takahiro_Hanyu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.2000.848652>
foaf:homepage <https://doi.org/10.1109/ISMVL.2000.848652>
dc:identifier DBLP conf/ismvl/HanyuKK00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.2000.848652 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiromitsu_Kimura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michitaka_Kameyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takahiro_Hanyu>
swrc:pages 423-429 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/HanyuKK00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/HanyuKK00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl2000.html#HanyuKK00>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.2000.848652>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:subject DRAM, multiple-valued logic, logic-in-memory, communication bottleneck, threshold operation, functional pass gate (xsd:string)
dc:title DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document