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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/HaradaBKF14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michitaka_Kameyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shintaro_Harada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xu_Bai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yoshichika_Fujioka>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.2014.45>
foaf:homepage <https://doi.org/10.1109/ISMVL.2014.45>
dc:identifier DBLP conf/ismvl/HaradaBKF14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.2014.45 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michitaka_Kameyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shintaro_Harada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xu_Bai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yoshichika_Fujioka>
swrc:pages 214-219 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/2014>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/HaradaBKF14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/HaradaBKF14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl2014.html#HaradaBKF14>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.2014.45>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document