Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/HasegawaHK05
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Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.
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Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.
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