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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rin_Suzuki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takashi_Hirayama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasuaki_Nishitani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL57333.2023.00038>
foaf:homepage <https://doi.org/10.1109/ISMVL57333.2023.00038>
dc:identifier DBLP conf/ismvl/HirayamaSYN23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL57333.2023.00038 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takashi_Hirayama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasuaki_Nishitani>
swrc:pages 153-157 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISMVL57333.2023.00038>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document