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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/HommaDAH07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Katsuhiko_Degawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Naofumi_Homma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takafumi_Aoki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tatsuo_Higuchi_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.2007.6>
foaf:homepage <https://doi.org/10.1109/ISMVL.2007.6>
dc:identifier DBLP conf/ismvl/HommaDAH07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.2007.6 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Katsuhiko_Degawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Naofumi_Homma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takafumi_Aoki>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tatsuo_Higuchi_0001>
swrc:pages 31 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/HommaDAH07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/HommaDAH07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl2007.html#HommaDAH07>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.2007.6>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document