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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/MuranakaAIM96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Michael_Miller>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Noriaki_Muranaka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shigenobu_Arai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shigeru_Imanishi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.1996.508342>
foaf:homepage <https://doi.org/10.1109/ISMVL.1996.508342>
dc:identifier DBLP conf/ismvl/MuranakaAIM96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.1996.508342 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._Michael_Miller>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Noriaki_Muranaka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shigenobu_Arai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shigeru_Imanishi>
swrc:pages 92-97 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/MuranakaAIM96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/MuranakaAIM96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl1996.html#MuranakaAIM96>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.1996.508342>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:subject Ternary logic, neuron MOSFET, product sum computation, systolic array (xsd:string)
dc:title A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document