Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/NatsuiAH02
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2002
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Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.
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multiple-valued logic, arithmetic circuits, evolutionary computation, genetic algorithms
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Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis.
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