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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/NiemannD22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philipp_Niemann_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rolf_Drechsler>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL52857.2022.00009>
foaf:homepage <https://doi.org/10.1109/ISMVL52857.2022.00009>
dc:identifier DBLP conf/ismvl/NiemannD22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL52857.2022.00009 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philipp_Niemann_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rolf_Drechsler>
swrc:pages 9-14 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ISMVL52857.2022.00009>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document