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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/ParkYYK04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Byoung_Hee_Yoon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Heung_Soo_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kwang_Sub_Yoon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soo_Jin_Park>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.2004.1319941>
foaf:homepage <https://doi.org/10.1109/ISMVL.2004.1319941>
dc:identifier DBLP conf/ismvl/ParkYYK04 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.2004.1319941 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Byoung_Hee_Yoon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Heung_Soo_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kwang_Sub_Yoon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Soo_Jin_Park>
swrc:pages 198-203 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/ParkYYK04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/ParkYYK04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl2004.html#ParkYYK04>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.2004.1319941>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document