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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ismvl/TengB05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_H.-Y._Teng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ronald_J._Bolton>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISMVL.2005.17>
foaf:homepage <https://doi.org/10.1109/ISMVL.2005.17>
dc:identifier DBLP conf/ismvl/TengB05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISMVL.2005.17 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_H.-Y._Teng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ronald_J._Bolton>
swrc:pages 276-281 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ismvl/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ismvl/TengB05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ismvl/TengB05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ismvl/ismvl2005.html#TengB05>
rdfs:seeAlso <https://doi.org/10.1109/ISMVL.2005.17>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ismvl>
dc:title Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document