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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/isnn/QiangCYG06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Qiang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xun_Gao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yang_Cao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuan-yuan_Yan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11760191%5F191>
foaf:homepage <https://doi.org/10.1007/11760191_191>
dc:identifier DBLP conf/isnn/QiangCYG06 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11760191%5F191 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Power Estimation of CMOS Circuits by Neural Network Macromodel. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Qiang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xun_Gao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yang_Cao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuan-yuan_Yan>
swrc:pages 1313-1318 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/isnn/2006-3>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isnn/QiangCYG06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isnn/QiangCYG06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isnn/isnn2006-3.html#QiangCYG06>
rdfs:seeAlso <https://doi.org/10.1007/11760191_191>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isnn>
dc:title Power Estimation of CMOS Circuits by Neural Network Macromodel. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document