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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donglin_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Meng_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wenqin_Sun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhiwei_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISOCC.2017.8368803>
foaf:homepage <https://doi.org/10.1109/ISOCC.2017.8368803>
dc:identifier DBLP conf/isocc/LiuZSW17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISOCC.2017.8368803 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label Optimization of clock mesh based on wire sizing variation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donglin_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Meng_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wenqin_Sun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhiwei_Zhang>
swrc:pages 129-130 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/isocc/LiuZSW17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isocc/LiuZSW17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/isocc/isocc2017.html#LiuZSW17>
rdfs:seeAlso <https://doi.org/10.1109/ISOCC.2017.8368803>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isocc>
dc:title Optimization of clock mesh based on wire sizing variation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document