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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donggu_Im>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hang-Geun_Jeong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jae-Hee_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/So-Hyeon_Park>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISOCC50952.2020.9333090>
foaf:homepage <https://doi.org/10.1109/ISOCC50952.2020.9333090>
dc:identifier DBLP conf/isocc/ParkLJI20 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISOCC50952.2020.9333090 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donggu_Im>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hang-Geun_Jeong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jae-Hee_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/So-Hyeon_Park>
swrc:pages 250-251 (xsd:string)
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owl:sameAs <http://dblp.rkbexplorer.com/id/conf/isocc/ParkLJI20>
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rdfs:seeAlso <https://doi.org/10.1109/ISOCC50952.2020.9333090>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/isocc>
dc:title Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document