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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispa/AbderazekSYS03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ben_A._Abderazek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Sowa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soichi_Shigeta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Yoshinaga>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F3-540-37619-4%5F26>
foaf:homepage <https://doi.org/10.1007/3-540-37619-4_26>
dc:identifier DBLP conf/ispa/AbderazekSYS03 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F3-540-37619-4%5F26 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
rdfs:label On the Design of a Register Queue Based Processor Architecture (FaRM-rq). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ben_A._Abderazek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Sowa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Soichi_Shigeta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Yoshinaga>
swrc:pages 248-262 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispa/2003>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispa/AbderazekSYS03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispa/AbderazekSYS03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispa/ispa2003.html#AbderazekSYS03>
rdfs:seeAlso <https://doi.org/10.1007/3-540-37619-4_26>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispa>
dc:title On the Design of a Register Queue Based Processor Architecture (FaRM-rq). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document