Designing a High Performance and Fault Tolerant Multistage Interconnection Network with Easy Dynamic Rerouting.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ispa/ChenGC04
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2004
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Designing a High Performance and Fault Tolerant Multistage Interconnection Network with Easy Dynamic Rerouting.
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Parallel computing, multistage interconnection network(MIN), fault tolerance, collision, performance, destination tag routing.
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Designing a High Performance and Fault Tolerant Multistage Interconnection Network with Easy Dynamic Rerouting.
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