Cache Management for Discrete Processor Architectures. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/ispa/Tu05>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jih-Fu_Tu>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1007%2F11576235%5F26>
foaf:homepage	<https://doi.org/10.1007/11576235_26>
dc:identifier	DBLP conf/ispa/Tu05 (xsd:string)
dc:identifier	DOI doi.org%2F10.1007%2F11576235%5F26 (xsd:string)
dcterms:issued	2005 (xsd:gYear)
rdfs:label	Cache Management for Discrete Processor Architectures. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jih-Fu_Tu>
swrc:pages	205-215 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/ispa/2005>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/ispa/Tu05/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/ispa/Tu05>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/ispa/ispa2005.html#Tu05>
rdfs:seeAlso	<https://doi.org/10.1007/11576235_26>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/ispa>
dc:subject	Discrete processor architectures, cache coherency, multithreading, memory latency, shared cache, write-invalidate (WI), and cache block. (xsd:string)
dc:title	Cache Management for Discrete Processor Architectures. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document