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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispacs/LaiCCS21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chiung-An_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun-Yu_Su>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jin-Yang_Lai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Lun_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISPACS51563.2021.9651130>
foaf:homepage <https://doi.org/10.1109/ISPACS51563.2021.9651130>
dc:identifier DBLP conf/ispacs/LaiCCS21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISPACS51563.2021.9651130 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Implement 32-bit RISC-V Architecture Processor using Verilog HDL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chiung-An_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun-Yu_Su>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jin-Yang_Lai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Lun_Chen>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispacs/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispacs/LaiCCS21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispacs/LaiCCS21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispacs/ispacs2021.html#LaiCCS21>
rdfs:seeAlso <https://doi.org/10.1109/ISPACS51563.2021.9651130>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispacs>
dc:title Implement 32-bit RISC-V Architecture Processor using Verilog HDL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document