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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispan/ChenK97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sun-Yuan_Kung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yen-Kuang_Chen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISPAN.1997.645125>
foaf:homepage <https://doi.org/10.1109/ISPAN.1997.645125>
dc:identifier DBLP conf/ispan/ChenK97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISPAN.1997.645125 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label An Operation Placement and Scheduling Scheme for Cache and Communication Localities in Fine-Grain Parallel Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sun-Yuan_Kung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yen-Kuang_Chen>
swrc:pages 390-396 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispan/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispan/ChenK97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispan/ChenK97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispan/ispan1997.html#ChenK97>
rdfs:seeAlso <https://doi.org/10.1109/ISPAN.1997.645125>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispan>
dc:subject Parallel compiler, operation placement and scheduling, performance optimization of instruction-level parallelism, VLSI array processor design methodology, multi-dimensional projection, multiprojection. (xsd:string)
dc:title An Operation Placement and Scheduling Scheme for Cache and Communication Localities in Fine-Grain Parallel Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document