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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispan/HoritaT99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Itsuo_Takanami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tadayoshi_Horita>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISPAN.1999.778929>
foaf:homepage <https://doi.org/10.1109/ISPAN.1999.778929>
dc:identifier DBLP conf/ispan/HoritaT99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISPAN.1999.778929 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
rdfs:label Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Itsuo_Takanami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tadayoshi_Horita>
swrc:pages 135-137 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispan/1999>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispan/HoritaT99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispan/HoritaT99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispan/ispan1999.html#HoritaT99>
rdfs:seeAlso <https://doi.org/10.1109/ISPAN.1999.778929>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispan>
dc:subject The 1 1/2-track switch model, mesh-connected processor arrays, reconfiguration, wefer scale integration, yield enhancement (xsd:string)
dc:title Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document