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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispan/NumataH96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Issei_Numata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Susumu_Horiguchi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FISPAN.1996.508985>
foaf:homepage <https://doi.org/10.1109/ISPAN.1996.508985>
dc:identifier DBLP conf/ispan/NumataH96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FISPAN.1996.508985 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Issei_Numata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Susumu_Horiguchi>
swrc:pages 221-227 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispan/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispan/NumataH96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispan/NumataH96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispan/ispan1996.html#NumataH96>
rdfs:seeAlso <https://doi.org/10.1109/ISPAN.1996.508985>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispan>
dc:subject fault tolerant computing; reconfigurable architectures; parallel architectures; multiprocessor interconnection networks; reconfiguration scheme; mesh-connected network; recursive shift; faulty processing elements; mesh arrays; redundant processing elements; fault tolerance; massively parallel system (xsd:string)
dc:title Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document