DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Hongzhong_Zheng>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Howard_David>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jiang_Lin>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zhao_Zhang_0010>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zhichun_Zhu>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FISPASS.2007.363740>
foaf:homepage	<https://doi.org/10.1109/ISPASS.2007.363740>
dc:identifier	DBLP conf/ispass/LinZZZD07 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FISPASS.2007.363740 (xsd:string)
dcterms:issued	2007 (xsd:gYear)
rdfs:label	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Hongzhong_Zheng>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Howard_David>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jiang_Lin>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Zhao_Zhang_0010>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Zhichun_Zhu>
swrc:pages	94-104 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1109/ISPASS.2007.363740>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/ispass>
dc:subject	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, power saving, multicore processor, interconnect structure, memory controller, DRAM chip, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency (xsd:string)
dc:title	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. (xsd:string)
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