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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/ChuW05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_C._N._Chu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yiu-Chung_Wong>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1055137.1055145>
foaf:homepage <https://doi.org/10.1145/1055137.1055145>
dc:identifier DBLP conf/ispd/ChuW05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1055137.1055145 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_C._N._Chu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yiu-Chung_Wong>
swrc:pages 28-35 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/ChuW05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/ChuW05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2005.html#ChuW05>
rdfs:seeAlso <https://doi.org/10.1145/1055137.1055145>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject rectilinear steiner minimal tree algorithm, routing, wirelength estimation (xsd:string)
dc:title Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document