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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/DanielOLLW02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chin_Siong_Ong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacob_White_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kwok_Hong_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Daniel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sok_Chay_Low>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F505388.505436>
foaf:homepage <https://doi.org/10.1145/505388.505436>
dc:identifier DBLP conf/ispd/DanielOLLW02 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F505388.505436 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Geometrically parameterized interconnect performance models for interconnect synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chin_Siong_Ong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacob_White_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kwok_Hong_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Daniel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sok_Chay_Low>
swrc:pages 202-207 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/DanielOLLW02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/DanielOLLW02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2002.html#DanielOLLW02>
rdfs:seeAlso <https://doi.org/10.1145/505388.505436>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject interconnect synthesis, parametrized model order reduction (xsd:string)
dc:title Geometrically parameterized interconnect performance models for interconnect synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document