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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/DengM01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wojciech_Maly>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yangdong_Deng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F369691.369763>
foaf:homepage <https://doi.org/10.1145/369691.369763>
dc:identifier DBLP conf/ispd/DengM01 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F369691.369763 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
rdfs:label Interconnect characteristics of 2.5-D system integration scheme. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wojciech_Maly>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yangdong_Deng>
swrc:pages 171-175 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2001>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/DengM01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/DengM01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2001.html#DengM01>
rdfs:seeAlso <https://doi.org/10.1145/369691.369763>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:subject 2.5-D system integration, VLSI, bounded sliceline grid, floorplanning, partition, placement, wirelength (xsd:string)
dc:title Interconnect characteristics of 2.5-D system integration scheme. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document