A routing approach to reduce glitches in low power FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ispd/DinhCW09
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2009
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A routing approach to reduce glitches in low power FPGAs.
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fpgas, glitch reduction, low power, path balancing, routing
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A routing approach to reduce glitches in low power FPGAs.
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