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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ispd/GoreTG21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ganesh_Gore>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pierre-Emmanuel_Gaillardon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xifan_Tang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3439706.3447047>
foaf:homepage <https://doi.org/10.1145/3439706.3447047>
dc:identifier DBLP conf/ispd/GoreTG21 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3439706.3447047 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ganesh_Gore>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pierre-Emmanuel_Gaillardon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xifan_Tang>
swrc:pages 135-142 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ispd/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ispd/GoreTG21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ispd/GoreTG21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ispd/ispd2021.html#GoreTG21>
rdfs:seeAlso <https://doi.org/10.1145/3439706.3447047>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ispd>
dc:title A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document